code wiki / _hdl_build / nx_pcb_render_gate.nx
nx_pcb_render_gate.nx
buildroot/runtime/_hdl_build/nx_pcb_render_gate.nx
about
nx_pcb_render_gate.nx -- GATE for the mechanistically-ACCURATE PCB visual. Routes a real net on the shared router,
renders it at TRUE scale (pitch=10 mil, trace=6 mil, scale=4 px/mil), and PROVES the drawing is dimensionally exact:
T1 DIMENSIONAL -- a vertical scan through the trace shows EXACTLY trace_width*scale = 24 copper pixels (a 6-mil
trace is exactly 6 mil wide on screen). The visual is a scale twin, not a cartoon. (the liar-kill)
T2 NO-FABRICATE -- an empty board renders ZERO copper (the render never invents copper that wasn't routed).
T3 DETERMINISM -- routing+rendering twice yields byte-identical images (#26 never-brick: reproducible).
T4 REFLECTS-ROUTE- the routed board has copper>0 driven by the ACTUAL route.
Writes knowledge/nx_pcb_render.ppm to eyeball. GREEN iff T1-T4. Sovereign integer raster. expect_exit: 0 license_tier: ORIGINAL
dependencies 4 imports · 0 importers
imports: nx_pcb_render.nxnx_pcb_autoroute.nxnx_png_write.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 14 | func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 15 | func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 16 | func fill(a: *i64, n: i64, v: i64) -> i64 { var i: i64=0; while i<n { a[i]=v; i=i+1 } return 0 } called by 1: main |
| 18 | func main() -> i64 |