nx_regalloc_linscan.nx

nx_regalloc_linscan.nx -- linear-scan register allocation, bits-up + PROVABLE. This is the keystone lever the ONGOING race vs C keeps pointing at: Nishi's stack/memory-resident codegen loads every operand and stores every result (the ~2x speed + ~6x code-density tax the race measured). Register allocation keeps live values in registers; only SPILLS touch memory. Built STANDALONE + proven first (NOT hand-patched into the protected self-hosting compiler -- a prior "g1 regalloc" attempt silently miscompiled high-pressure functions; we prove soundness here, then the loop absorbs it into codegen under governance). Algorithm: Poletto & Sarkar, "Linear Scan Register Allocation," ACM TOPLAS 1999 (the alternative is Chaitin graph-coloring, SIGPLAN 1982; linear scan is faster and good enough -- the right fit for a spore that re-derives its stack on deploy). Model IR: a straight-line block of n instructions; instruction i DEFINES virtual register i and USES up to two prior vregs (u0[i], u1[i]; -1 = none). The live interval of vreg v is [v (its def), last_use[v]]. Linear scan allocates nreg physical registers across the intervals, spilling the farthest-future interval when it runs out (the standard heuristic).