nx_riscv_spec_oracle_gate.nx
buildroot/runtime/nx_riscv_spec_oracle_gate.nx
about
nx_riscv_spec_oracle_gate.nx -- THE ORACLE ROW FOR `nishios`: corroborate the mcause exception codes
our kernel gates depend on against the OFFICIAL RISC-V PRIVILEGED SPECIFICATION -- a document WE DID
NOT WRITE.
WHY: nx_evidence_verdict.nx clause 5 TRIANGULATION needs >=2 method classes with >=1 MECHANISTIC, and
defines ORACLE as agreement with external ground truth. Every nishios gate is MECH and SELF-AUTHORED,
so the domain carried ONE class and min_classes=2 made PROVEN unreachable. This is the second class.
THE SUBJECT: knowledge/specs/EXTERNAL-riscv-priv-machine.adoc -- the machine-level chapter of the
RISC-V ISA manual, fetched 2026-08-15 from riscv/riscv-isa-manual (main) over the sovereign HTTPS
stack, preamble stripped, copy byte-verified. 173,346 B of CLEAN ASCIIDOC SOURCE.
WHY NOT THE PDF -- MEASURED, AND IT IS THE WHOLE REASON THIS FILE EXISTS. The official v1.12 PDF was
fetched first and converted with nx_pdf_text. Its text layer is KERNED, so extraction SPLITS WORDS
(`Privileged Arc hitectures`, `this do cumen twas`) and drops ligatures (`simpli???ed`). Grepping THAT
artifact for "Environment call from U-mode" returned 0 matches, corpus_complete=1 -- while the spec
plainly contains it, at line 1875 of THIS file.
******A DEGRADED RENDERING OF A CORRECT SOURCE PRODUCES CONFIDENT FALSE ABSENCES, AND AN ORACLE BUILT
ON IT WOULD ACCUSE THE ESTATE OF DEVIATING FROM A STANDARD IT ACTUALLY FOLLOWS. A FALSE RED AGAINST AN
EXTERNAL AUTHORITY IS THE MOST CREDIBLE WRONG ANSWER AVAILABLE. Two renderings of ONE document
disagreeing is what located the defect in the RENDERING rather than in the spec or in us.
WHAT IT CHECKS, and the CEILING STATED PLAINLY. The spec's exception table is AsciiDoc: a column of
codes and a parallel column of descriptions. This gate does NOT claim to parse that table. It asserts
the STRUCTURE our gates actually depend on:
T1 both mcause descriptions exist in the official text at all
T2 U-mode precedes M-mode => mcause(U) < mcause(M), i.e. they are DISTINCT and ordered
T3 exactly TWO description entries sit between them (S-mode, _Reserved_)
=> mcause(M) - mcause(U) == 3, which with the U=8 anchor pins M=11
That is the RELATIONSHIP _umode_gate relies on (ecall-from-U => 8, its MPP=M control => 11).
It pins ORDER and GAP against external text; it does not re-derive the absolute integers from the
table's code column. **CORROBORATION, NEVER DERIVATION** -- the same ceiling the virtio oracle carries.
exit: gv_verdict (0 GREEN / 1 RED / 3 SKIP) license_tier: ORIGINAL. Read-only. No hw writes (Rule 26).
dependencies 2 imports · 0 importers
imports: nx_syscalls.nxnx_gate_verdict.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 37 | const RO_SPEC: *u8 = "knowledge/specs/EXTERNAL-riscv-priv-machine.adoc" |
| 38 | const RO_U: *u8 = "Environment call from U-mode" |
| 39 | const RO_S: *u8 = "Environment call from S-mode" |
| 40 | const RO_M: *u8 = "Environment call from M-mode" |
| 43 | const RO_BOGUS: *u8 = "Environment call from Q-mode" |
| 45 | const RO_EXPECT_GAP: i64 = 3 |
| 49 | const RO_SUPER: *u8 = "knowledge/specs/EXTERNAL-riscv-priv-supervisor.adoc" |
| 50 | const RO_SV39ROW: *u8 = "Sv39 |Page-based 39-bit virtual addressing" |
| 51 | const RO_SV39_MODE: i64 = 8 |
| 52 | const RO_SV48_MODE: i64 = 9 |
| 59 | const RO_LEVELS: *u8 = "[#norm:Sv39_levels]#three-level page table#" |
| 60 | const RO_VPN: *u8 = "[#norm:Sv39_vpn_sz]#27-bit VPN#" |
| 61 | const RO_PPN: *u8 = "[#norm:satp_ppn_sv39_sz]#44-bit PPN#" |
| 63 | const RO_BOGUS_NORM: *u8 = "[#norm:Sv39_qqq]#" |
| 69 | const RO_PTEV: *u8 = "If _pte_._v_=0, or if _pte_._r_=0 and _pte_._w_=1" |
| 70 | const RO_PTEFAULT: *u8 = "stop and raise a page-fault exception" |
| 71 | const RO_BOGUS_PTE: *u8 = "If _pte_._z_=0" |
| 72 | const RO_NL: i64 = 10 |
functions
| 74 | func ro_p(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 } |
| 75 | func ro_n(v: i64) -> i64 |
| 88 | func ro_len(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } return n } called by 1: ro_find |
| 92 | func ro_line_first_int(buf: *u8, off: i64) -> i64 called by 1: main |
| 117 | func ro_find(buf: *u8, n: i64, lit: *u8) -> i64 |
| 131 | func ro_lines_between(buf: *u8, a: i64, b: i64) -> i64 called by 1: main |
| 138 | func main() -> i64 |