code wiki / riscv

topic: riscv

12 modules sharing the riscv name family (derived from the tree's prefix discipline).

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nx_riscv.nxRV64 codegen backend, in NishiLang. 282164
nx_riscv_codegen.nxSOVEREIGN RISC-V backend, RUNG 4: IR -> RISC-V CODEGEN. Now on the GENERAL nx_riscv_lib662
nx_riscv_decode.nxSOVEREIGN RISC-V backend RUNG 1b: our own rv64im DECODER / round-trip oracle. Now on the712
nx_riscv_elf.nxSOVEREIGN RISC-V backend RUNG 2: our own ELF64 writer. Now on the GENERAL nx_riscv_lib561
nx_riscv_emit.nxSOVEREIGN RISC-V backend RUNG 1: our own rv64im encoder. Now on the GENERAL nx_riscv_lib574
nx_riscv_emu.nxSOVEREIGN RISC-V backend, RUNG 5: execute the ELF our writer emitted. Now on the GENERAL431
nx_riscv_gate.nxSOVEREIGN verifier for the whole RISC-V toolchain. The ECOSYSTEM checks itself: this organ615
nx_riscv_lib.nxGENERAL SOVEREIGN RISC-V CAPABILITIES (the shared ecosystem library for the rv64im toolchain).13533
nx_riscv_loop.nxSOVEREIGN RISC-V backend, RUNG 3: CONTROL FLOW. Now uses the GENERAL nx_riscv_lib for the703
riscv.nxalias stub.280
riscv_fp_test.nxself-test for rv_emit_fbinop (F-extension). 2662
riscv_test.nxself-test for riscv.nx. 311