nx_rvc_run_suite.nx

nx_rvc_run_suite.nx -- nishios NO3: run the published RISC-V architectural test suite on the SOVEREIGN rv64im_min_sim and report the pass count PER TEST GROUP against the repo's Spike-generated reference signatures. Watch symbol: rvc_run_suite. THE SUBJECT is our sim (rv64im_min_sim via nx_bootcap's ONE machine composition). The corpus is third-party (riscv-non-isa/riscv-arch-test 2.7.4): the test .S sources are assembled by an ORACLE/BUILD-TOOL gcc on the laptop (never on the sovereign chain) and the .reference_output signatures are the repo's own Spike-generated vectors. So this gate compares OUR execution against a published third-party reference -- exactly what "architectural compliance" means. Corpus is pinned (riscv_arch_test.pin, pipe-row grammar, sha256 per file) so the population is fixed + citable. COMPLETION MARKER: RVMODEL_HALT writes 1 to the `tohost` symbol (a RAM word) then spins. We poll that word; when nonzero the test has signalled done. Then we dump [begin_signature, end_signature) as little-endian 32-bit words and compare, word for word, against the reference. VERDICTS (never one percentage; per group, partition printed and summed): PASS completed (tohost set) AND every signature word matches FAIL completed but a signature word differs (the sim executed something wrong) UNSUPPORTED did not complete: an illegal/unimplemented instruction halted it, or it never wrote tohost within the step budget (a hang) -- reported apart from FAIL because it is NOT "the sim computed a wrong value", it is "the sim cannot run this test". A memory big enough for the whole image is DERIVED from the pinned mem_end (the linker's _end), never guessed: the branch tests (jal/beq/...) place their signature ~586 KB above mem_base, so the fixed 64 KB boot RAM cannot hold them -- nx_bootcap.bootcap_machine_mem takes the size (one composition). license_tier: ORIGINAL (the debugger/assembler/references are third-party oracles; nothing of them ships)