code wiki / _hdl_build / nx_cpuid_lib.nx

nx_cpuid_lib.nx

buildroot/runtime/_hdl_build/nx_cpuid_lib.nx

6343 B135 linesdepth 2pulls 2 transitivereach 2 importersview sourcekind library
docsdependenciesstructsconstsfunctions

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nx_cpuid_lib.nx -- PURE decode of x86-64 cpuid(7,0):EBX, the structured extended-feature register. WHY: nx_prim_gap reported cpu-feature-detect as MISSING across all 256 registry primitives, which read as 'the ecosystem cannot see its own silicon'. THAT WAS A DISCOVERY FAILURE, NOT A CAPABILITY ONE -- runtime/nx_cpu_features.nx already does REAL cpuid via the __cpuid_ebx intrinsic (nx_types OP_CPUID_EBX =133, emitted as raw bytes 0F A2 because sovereign nxasm has no cpuid mnemonic). But it exposes only THREE bits (BMI2/ADX/both) out of a register that ALREADY CARRIES AVX2, the whole AVX-512 family, SHA, BMI1, RDSEED, ADX and CLFLUSHOPT. The data was fetched and thrown away. LAW: a capability that no registry can see is indistinguishable from one that does not exist. EVERYTHING HERE IS PURE (ebx value in -> answer out). That is deliberate and load-bearing: it lets the gate prove AVX-512 decoding CORRECT ON HARDWARE THAT HAS NO AVX-512, by feeding synthetic registers. A detector you can only test on silicon you own is a detector you cannot trust for future silicon -- and future silicon is the entire point of this primitive. license_tier: ORIGINAL Read-only. No hw writes (Rule 26).

dependencies 1 imports · 2 importers

nx_syscalls.nx nx_cpuid_lib.nx nx_cpuid.nx nx_cpuid_gate.nx

imports: nx_syscalls.nx

imported by: nx_cpuid.nxnx_cpuid_gate.nx

structs

none

consts

19const CF_BIT_FSGSBASE: i64 = 0
20const CF_BIT_BMI1: i64 = 3
21const CF_BIT_AVX2: i64 = 5
22const CF_BIT_SMEP: i64 = 7
23const CF_BIT_BMI2: i64 = 8
24const CF_BIT_AVX512F: i64 = 16
25const CF_BIT_AVX512DQ: i64 = 17
26const CF_BIT_RDSEED: i64 = 18
27const CF_BIT_ADX: i64 = 19
28const CF_BIT_SMAP: i64 = 20
29const CF_BIT_CLFLUSHOPT: i64 = 23
30const CF_BIT_AVX512CD: i64 = 28
31const CF_BIT_SHA: i64 = 29
32const CF_BIT_AVX512BW: i64 = 30
33const CF_BIT_AVX512VL: i64 = 31
46const CF_BYTE_MASK: i64 = 255
47const CF_CLFLUSH_UNIT: i64 = 8
64const CF_TIER_SCALAR: i64 = 0
65const CF_TIER_AVX2: i64 = 1
66const CF_TIER_AVX512: i64 = 2

functions

49func cf_cache_line(ebx1: i64) -> i64
called by 1: main
56func cf_logical_procs(ebx1: i64) -> i64
called by 1: main
69func cf_bit(ebx: i64, b: i64) -> i64
76func cf_avx2(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX2) }
called by 3: mainmaincf_simd_tier calls 1: cf_bit
77func cf_bmi1(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_BMI1) }
called by 1: main calls 1: cf_bit
78func cf_bmi2(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_BMI2) }
called by 2: mainmain calls 1: cf_bit
79func cf_adx(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_ADX) }
called by 2: mainmain calls 1: cf_bit
80func cf_sha(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_SHA) }
called by 2: mainmain calls 1: cf_bit
81func cf_rdseed(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_RDSEED) }
called by 1: main calls 1: cf_bit
82func cf_clflushopt(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_CLFLUSHOPT) }
called by 1: main calls 1: cf_bit
83func cf_avx512f(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512F) }
called by 3: mainmaincf_simd_tier calls 1: cf_bit
84func cf_avx512dq(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512DQ) }
called by 2: mainmain calls 1: cf_bit
85func cf_avx512cd(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512CD) }
called by 1: main calls 1: cf_bit
86func cf_avx512bw(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512BW) }
called by 2: mainmain calls 1: cf_bit
87func cf_avx512vl(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512VL) }
called by 2: mainmain calls 1: cf_bit
92func cf_simd_tier(ebx: i64) -> i64
called by 2: mainmain calls 2: cf_avx2cf_avx512f
105func cf_isdelim(c: i64) -> i64
called by 1: cf_flag
112func cf_flag(buf: *u8, n: i64, tok: *u8) -> i64
called by 2: ci_rowmain calls 1: cf_isdelim