code wiki / _hdl_build / nx_cpuid_lib.nx
nx_cpuid_lib.nx
buildroot/runtime/_hdl_build/nx_cpuid_lib.nx
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nx_cpuid_lib.nx -- PURE decode of x86-64 cpuid(7,0):EBX, the structured extended-feature register.
WHY: nx_prim_gap reported cpu-feature-detect as MISSING across all 256 registry primitives, which read
as 'the ecosystem cannot see its own silicon'. THAT WAS A DISCOVERY FAILURE, NOT A CAPABILITY ONE --
runtime/nx_cpu_features.nx already does REAL cpuid via the __cpuid_ebx intrinsic (nx_types OP_CPUID_EBX
=133, emitted as raw bytes 0F A2 because sovereign nxasm has no cpuid mnemonic). But it exposes only
THREE bits (BMI2/ADX/both) out of a register that ALREADY CARRIES AVX2, the whole AVX-512 family, SHA,
BMI1, RDSEED, ADX and CLFLUSHOPT. The data was fetched and thrown away.
LAW: a capability that no registry can see is indistinguishable from one that does not exist.
EVERYTHING HERE IS PURE (ebx value in -> answer out). That is deliberate and load-bearing: it lets the
gate prove AVX-512 decoding CORRECT ON HARDWARE THAT HAS NO AVX-512, by feeding synthetic registers.
A detector you can only test on silicon you own is a detector you cannot trust for future silicon --
and future silicon is the entire point of this primitive.
license_tier: ORIGINAL Read-only. No hw writes (Rule 26).
dependencies 1 imports · 2 importers
imports: nx_syscalls.nx
imported by: nx_cpuid.nxnx_cpuid_gate.nx
structs
| none |
consts
| 19 | const CF_BIT_FSGSBASE: i64 = 0 |
| 20 | const CF_BIT_BMI1: i64 = 3 |
| 21 | const CF_BIT_AVX2: i64 = 5 |
| 22 | const CF_BIT_SMEP: i64 = 7 |
| 23 | const CF_BIT_BMI2: i64 = 8 |
| 24 | const CF_BIT_AVX512F: i64 = 16 |
| 25 | const CF_BIT_AVX512DQ: i64 = 17 |
| 26 | const CF_BIT_RDSEED: i64 = 18 |
| 27 | const CF_BIT_ADX: i64 = 19 |
| 28 | const CF_BIT_SMAP: i64 = 20 |
| 29 | const CF_BIT_CLFLUSHOPT: i64 = 23 |
| 30 | const CF_BIT_AVX512CD: i64 = 28 |
| 31 | const CF_BIT_SHA: i64 = 29 |
| 32 | const CF_BIT_AVX512BW: i64 = 30 |
| 33 | const CF_BIT_AVX512VL: i64 = 31 |
| 46 | const CF_BYTE_MASK: i64 = 255 |
| 47 | const CF_CLFLUSH_UNIT: i64 = 8 |
| 64 | const CF_TIER_SCALAR: i64 = 0 |
| 65 | const CF_TIER_AVX2: i64 = 1 |
| 66 | const CF_TIER_AVX512: i64 = 2 |
functions
| 49 | func cf_cache_line(ebx1: i64) -> i64 called by 1: main |
| 56 | func cf_logical_procs(ebx1: i64) -> i64 called by 1: main |
| 69 | func cf_bit(ebx: i64, b: i64) -> i64 |
| 76 | func cf_avx2(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX2) } |
| 77 | func cf_bmi1(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_BMI1) } |
| 78 | func cf_bmi2(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_BMI2) } |
| 79 | func cf_adx(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_ADX) } |
| 80 | func cf_sha(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_SHA) } |
| 81 | func cf_rdseed(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_RDSEED) } |
| 82 | func cf_clflushopt(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_CLFLUSHOPT) } |
| 83 | func cf_avx512f(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512F) } |
| 84 | func cf_avx512dq(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512DQ) } |
| 85 | func cf_avx512cd(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512CD) } |
| 86 | func cf_avx512bw(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512BW) } |
| 87 | func cf_avx512vl(ebx: i64) -> i64 { return cf_bit(ebx, CF_BIT_AVX512VL) } |
| 92 | func cf_simd_tier(ebx: i64) -> i64 |
| 105 | func cf_isdelim(c: i64) -> i64 called by 1: cf_flag |
| 112 | func cf_flag(buf: *u8, n: i64, tok: *u8) -> i64 |