nx_q4k_dot_simd_lib.nx
buildroot/runtime/nx_q4k_dot_simd_lib.nx
about
nx_q4k_dot_simd_lib.nx -- the fused Q4_K SIMD dot as a LIBRARY (extracted 2026-09-02 from nx_q4k_dot_simd.nx,
which keeps its bench main and now imports this; the extraction is proven by that organ rebuilding to the
banked sha). Consumers: nx_nofloat_q4k (LM4 resident-quant decode). Kernel unchanged: per sub-block
dot += d1*sq - m0*sc with sq = sum q*col via vpmaddwd (q i16 0..15, col i16), sc from a precomputed
activation-only table. Returns sum over the row of W_Q24 * col_i16 (weight in Q24 fixed point).
license_tier: ORIGINAL
dependencies 6 imports · 5 importers
imports: nx_syscalls.nxnx_tier.nxnx_le.nxnx_tensor.nxnx_gguf.nxnx_gguf_load.nx
imported by: nx_nofloat_q4k.nxnx_nofloat_q4k_gate.nxnx_q4k_dot_simd.nxnx_q4k_dot_simd2_lib.nxnx_q4k_simd2_gate.nx
structs
| none |
consts
| 21 | const DS_M_NIB: i64 = 0x0F0F0F0F0F0F0F0F // low nibble of every byte |
| 22 | const DS_M_LO32: i64 = 0xFFFFFFFF // the 4 bytes a spread turns into 4 lanes |
| 23 | const DS_M_SPREAD16: i64 = 0x0000FFFF0000FFFF // after (v | v<<16): bytes 0,1 stay, bytes 2,3 land at 32..47 |
| 24 | const DS_M_SPREAD8: i64 = 0x00FF00FF00FF00FF // after (v | v<<8): one byte per 16-bit lane |
| 25 | const DS_HALF_BITS: i64 = 32 |
| 26 | const DS_NIB_BITS: i64 = 4 |
| 27 | const DS_QS_U64_PER_GROUP: i64 = 4 // 32 qs bytes per sub-block pair = four u64 reads |
functions
| 30 | func ds_spread4(v: i64) -> i64 |
| 37 | func ds_pack4(a: i64, b: i64, c: i64, d: i64) -> i64 |
| 41 | func ds_hsum(acc: *i64) -> i64 |
| 57 | func nx_q4k_sc_precompute(col_q10: *i64, n_blocks: i64, sc_pre: *i64) -> i64 |
| 74 | func nx_q4k_dot_simd(buf: *u8, base_off: i64, n_blocks: i64, col_i16: *i64, called by 2: mainmain calls 6: _gguf_f16_to_q24nx_le_read_u16nx_le_read_u8nx_le_read_u64ds_spread4ds_hsum |