nx_q4k_simd2_gate.nx

nx_q4k_simd2_gate.nx -- the REFEREE for __q4k_unpack32s (the nx_cc intrinsic) and nx_q4k_dot_simd2 (2026-09-02, LM4c). The intrinsic is proven at TWO levels. (1) LANE LEVEL: on packed bytes whose nibbles and scales are chosen so every expected lane is known, out[k] must equal (byte_k & 15) * sc_lo and out[32+k] must equal (byte_k >> 4) * sc_hi for all 64 lanes, including the extreme lane value 15*63 = 945 (no lane carry) and a zero scale; and a run over 5000 pseudo-random byte blocks must agree lane-for-lane with the scalar spread+multiply nx_q4k_dot_simd_lib already trusts (ds_spread4). (2) DOT LEVEL: on 200 pseudo-random Q4_K super-block rows with real-shaped d, dmin, scales and mins, nx_q4k_dot_simd2 must return EXACTLY what nx_q4k_dot_simd returns (both are exact integer functions of the same bytes) and exactly what the scalar reference nx_q4k_dot_row_col returns. Neg-controls: a corrupted lane must NOT match (the lane tooth can fail) and a flipped nibble byte must change the dot (the dot tooth can fail). A timing line reports simd2 vs simd over the same rows (a number, never a verdict -- the decode benchmark is the speed ruler). nx_q4k_simd2_gate (no args; needs a compiler that knows __q4k_unpack32s, else it does not build) license_tier: ORIGINAL. Writes nothing. No hw writes.