nx_f64.nx

nx_f64.nx -- IEEE 754 binary64 (double-precision float) bits-up. L5 of the bits-up numeric tower (docs/NISHI_BITS_UP_NUMERIC_TOWER_ROADMAP.md) and ME0 keystone of the math-engine-exceed ladder (DLMF/GAMS-class special functions all sit on binary64 or better). Pure i64 substrate: no libm, no soft-float stubs, no compiler builtins. Bit layout (IEEE 754-2019 binary64): bit 63: sign bits 62..52: exponent (biased 1023; 0 = subnormal/zero; 2047 = inf/NaN) bits 51..0: mantissa (52 bits; implicit leading 1 for normals) Storage: an f64 value IS the i64 holding its bit pattern (full width -- unlike f32-in-low-32-bits, raw f64 i64s go negative when sign=1; all field extraction masks after shifting, so arithmetic-shift fill is harmless). The 53x53-bit significand product (106 bits) exceeds i64. We split each significand 26/27 bits so every partial product and partial sum stays under 2^63 (verified at runtime by _f64_probe before this file was authored). CORRECTNESS BAR (above the f32 v1 family): subnormal inputs are pre-normalized, subnormal outputs are denormalized BEFORE rounding (no double-rounding), so add/sub/mul here are correctly rounded round-to- nearest-even across the whole domain. Gate: _f64_gate_authored KATs vs hardware-IEEE oracle bit patterns. File layout note: division lives in nx_f64_div.nx and sqrt in nx_f64_sqrt.nx, mirroring the f32 family split that sidesteps the nxc2 same-file mul+div codegen quirk (see nx_f32_div.nx header). genealogy_id: ieee754_2019_binary64 + goldberg_1991_csur + muller_handbook_fp_2018 (referenced, not copied) license_tier: ORIGINAL